Title :
Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems
Author :
Hasan, Syed Rafay ; Bélanger, Normand ; Savaria, Yvon ; Ahmad, M. Omair
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada
Abstract :
This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP) due to aggressor-to-quiet-line crosstalk (AQX) in asynchronous handshake schemes can only be observed through circuit-level analysis/simulation. In this paper, circuit-level analysis is first performed to prove that even optimized conventional asynchronous circuits allow crosstalk glitches produced over moderate-length interconnects (1.5 mm) to propagate. This is a precursor to a more problematic crosstalk glitch occurrence due to further scaling of technologies. To warn the digital designers from GP due to AQX, a novel modeling technique is proposed. This modeling method works at the logic level to facilitate asserting asynchronous interface robustness to crosstalk glitches. This model can accurately identify the possibility of intrinsic (to the asynchronous interface) crosstalk GP in asynchronous circuits at the logic level and, hence, provides a foundation to formally verify such circuits. To our knowledge, this is the first work on modeling GP due to AQX at the logic level for asynchronous circuits.
Keywords :
asynchronous circuits; crosstalk; logic design; aggressor-to-quiet-line crosstalk; asynchronous handshake schemes; asynchronous interface circuits; asynchronous protocols; catastrophic effect; circuit-level analysis-simulation; crosstalk glitch propagation modeling; global asynchronous locally synchronous systems; moderate-length interconnects; representative circuit; system failure; Asynchronous interface; crosstalk; deep submicrometer (DSM); multiple clock domains (MCDs);
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2009.2038553