Active GHz clock network using distributed PLLs

Author

Gutnik, Vadim ; Chandrakasan, Anantha P.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

Volume

35

Issue

11

fYear

2000

Firstpage

1553

Lastpage

1560

Abstract

A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested. Undesirable large-signal stable (mode-locked) states dictate the transfer characteristic of the phase detectors; a matrix formulation of the linearized system allows direct calculation of system poles for any desired oscillator configuration. A 16-oscillator 1.3-GHz distributed clock network in 0.35-/spl mu/m CMOS is presented here.

Keywords

CMOS digital integrated circuits; active networks; circuit stability; clocks; digital phase locked loops; integrated circuit design; poles and zeros; synchronisation; timing jitter; voltage-controlled oscillators; 0.35 mum; 1.3 GHz; 16-oscillator distributed clock network; CMOS; VCO; active GHz clock network; differential ring oscillator; distributed PLLs; dynamic mismatch; large-signal stable states; linearized system; matrix formulation; mode-locked states; multiple synchronized phase-locked loops; network stability; oscillator configuration; phase detectors; random skew; static mismatch; synchronization; system poles; transfer characteristic; Circuit testing; Clocks; Delay; Detectors; Jitter; Oscillators; Phase detection; Phase locked loops; Synchronization; Wire;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.881199

Filename

881199