Title :
A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"
Author :
Saeki, Takanori ; Mitsuishi, Masafumi ; Iwaki, Hiroaki ; Tagishi, Mitsuaki
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array structure of short-circuit-current-suppression interpolators. The circuits have been fabricated with a 0.25-/spl mu/m digital CMOS and operated in any condition where digital CMOS circuits operate. Measured results have achieved 1.3 clock cycle lock time and cycle-to-cycle jitter suppression characteristics. The circuits have been verified in 622-Mb/s clock and data recovery that satisfied the ITU-T G.958 jitter tolerance specification.
Keywords :
CMOS digital integrated circuits; clocks; interpolation; multiplying circuits; timing jitter; 0.25 mum; 1.3-cycle lock-in time; 622 Mbit/s; ITU-T G.958 jitter tolerance specification; array structure; clock cycle lock time; clock on demand; clock recovery; cycle-to-cycle jitter suppression characteristics; data recovery; digital CMOS; direct clock cycle interpolation; nonPLL/DLL clock multiplier; short-circuit-current-suppression interpolators; CMOS digital integrated circuits; Clocks; Delay lines; Frequency conversion; Interpolation; Jitter; Phase locked loops; Power generation; Time measurement; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
