Title :
A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation
Author :
Yeung, Evelina ; Horowitz, Mark A.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
This paper describes voltage and timing margins and design trade-offs in low-cost parallel links. Results from a transceiver prototype demonstrate that per-pin skew compensation improves timing margins in these parallel links and can be implemented with reasonable cost overhead. Single-ended and simultaneous bidirectional links are viable alternatives to the traditional differential and unidirectional systems-these links require fewer pins and wires for the same bandwidth, and the additional noise sources, while significant, can be managed by careful circuit and package design.
Keywords :
CMOS digital integrated circuits; delay lock loops; error compensation; integrated circuit design; integrated circuit noise; parallel architectures; timing jitter; transceivers; 0.35 mum; 2.4 Gb/s/pin simultaneous bidirectional parallel link; 2.4 Gbit/s; CMOS process; core DLL; design trade-offs; low-cost parallel links; package design; per-pin skew compensation; source-synchronous point-to-point parallel links; timing error; timing margins; transceiver prototype; voltage margins; voltage noise; Bandwidth; Circuit noise; Costs; Packaging; Pins; Prototypes; Timing; Transceivers; Voltage; Wires;
Journal_Title :
Solid-State Circuits, IEEE Journal of
