A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

Author

Takeda, Koichi ; Aimoto, Yoshiharu ; Nakamura, Noritsugu ; Toyoshima, Hideo ; Iwasaki, Takahiro ; Noda, Kenji ; Matsui, Koujirou ; Itoh, Shinya ; Masuoka, Sadaaki ; Horiuchi, Tadahiko ; Nakagawa, Atsushi ; Shimogawa, Kenju ; Takahashi, Hiroyuki

Author_Institution

Dept. of Syst. Devices & Fundamental Res., NEC Corp., Kanagawa, Japan

Volume

35

Issue

11

fYear

2000

Firstpage

1631

Lastpage

1640

Abstract

We have used a 5-metal 0.18-/spl mu/m CMOS logic process to develop a 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. The macro contains: (1) end-point dual-pulse drivers for accurate timing control; (2) a wordline-voltage-level compensation circuit for stable data retention; and (3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also developed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CMOS process using 0.13-/spl mu/m gate length.

Keywords

CMOS memory circuits; SRAM chips; error compensation; high-speed integrated circuits; integrated circuit design; low-power electronics; timing; 0.13 mum; 0.18 mum; 1.8 V; 16 Mbit; 400 MHz; 500 MHz; CMOS logic process; all-adjoining twisted bitline scheme; bitline coupling capacitance; end-point dual-pulse drivers; gate length; high-speed access; loadless CMOS four-transistor SRAM macro; stable data retention; supply voltage; timing control; wordline-voltage-level compensation circuit; CMOS logic circuits; CMOS process; Capacitance; Coupling circuits; Driver circuits; FETs; National electric code; Random access memory; Timing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.881209

Filename

881209