An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin

Author

Pilo, Harold ; Allen, Archie ; Covino, Jim ; Hansen, Patrick R. ; Lamphier, Steve ; Murphy, Chris ; Traver, Terry ; Yee, Pui

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

Volume

35

Issue

11

fYear

2000

Firstpage

1641

Lastpage

1647

Abstract

This paper describes an 833-MHz 18-Mb CMOS SRAM with a 1.67-Gb/s/pin data rate. Issues that had to be overcome from previous-generation SRAMs to meet the performance goals are addressed. The SRAM has been successfully fabricated using a 0.18-/spl mu/m CMOS process with copper interconnects. It operates in two user-selectable double-data-rate modes (DDR and DDR2) and consumes 1.5 W of power at 833 MHz. In addition to the performance benefits resulting from this 0.18-/spl mu/m copper technology, architecture improvements, a data-to-echo-clock tracking system, and data symmetric output drivers made possible the high frequency of operation.

Keywords

CMOS memory circuits; SRAM chips; high-speed integrated circuits; low-power electronics; memory architecture; 0.18 mum; 1.5 W; 1.67 Gbit/s; 1.67-Gb/s/pin data rate; 18 Mbit; 833 MHz; CMOS SRAM; Cu interconnects; DDR; DDR2; architecture improvements; data symmetric output drivers; data-to-echo-clock tracking system; high frequency of operation; power consumption; user-selectable double-data-rate mode; CMOS process; Clocks; Copper; Decoding; Driver circuits; Frequency; Integrated circuit interconnections; Packaging; Random access memory; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.881210

Filename

881210