Title :
40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory
Author :
Campardo, Giovanni ; Micheloni, Rino ; Commodaro, Stefano ; Yero, Emilio ; Zammattio, Matteo ; Mognoni, Sabina ; Sacco, Andrea ; Picca, Massimiliano ; Manstretta, Alessandro ; Scotti, Marco ; Motta, Ilaria ; Golla, C. ; Pierin, Andrea ; Bez, Roberto ; Gro
Author_Institution :
Memory Product Group, STMicroelectronics, Milan, Italy
Abstract :
This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell) NOR-type channel-hot-electron (CHE) programmed flash memory fabricated in 0.18-/spl mu/m shallow-trench isolation CMOS technology. The device (die size 40 mm/sup 2/) is organized in 64 1-Mb sectors. Hierarchical column and row decoding ensures complete isolation between different sectors during any operation, thereby increasing device reliability while still providing layout area optimization. Staircase gate-voltage programming is used to achieve narrow threshold-voltage distributions. The same program throughput as for bilevel CHE-programmed memories is obtained, thanks to parallel programming. A mixed balanced/unbalanced sensing approach allows efficient use of the available threshold window. Asynchronous (130-ns access time) and burst-mode (up to 50-MHz data rate) reading is possible. Both column and row redundancy is provided to ensure extended failure coverage. Error correction code techniques, correcting 1 failed over 32 data cells, are also integrated.
Keywords :
CMOS memory circuits; PLD programming; error correction codes; flash memories; isolation technology; 0.18 mum; 130 ns; 3 V; 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory; 50 MHz; 64 Mbit; NOR-type channel-hot-electron programmed flash memory; access time; asynchronous reading; burst-mode reading; column redundancy; device reliability; die size; error correction code techniques; failure coverage; hierarchical column decoding; hierarchical row decoding; layout area optimization; mixed balanced/unbalanced sensing approach; narrow threshold-voltage distributions; parallel programming; row redundancy; shallow-trench isolation CMOS technology; staircase gate-voltage programming; threshold window; CMOS technology; Channel hot electron injection; Decoding; Error correction codes; Fabrication; Flash memory; Isolation technology; Parallel programming; Throughput; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
