An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM)

Author

Agata, Yasuhiro ; Motomochi, Kenji ; Fukushima, Yoshifumi ; Shirahama, Masanori ; Kurumada, Marefusa ; Kuroda, Naoki ; Sadakata, Hiroyuki ; Hayashi, Kohtaro ; Yamada, Toshio ; Takahashi, Kazunari ; Fujita, Tsutomu

Author_Institution

Adv. LSI Technol. Dev. Centre, Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

Volume

35

Issue

11

fYear

2000

Firstpage

1668

Lastpage

1672

Abstract

A novel fast random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM) has been developed. The macro exploits three key circuit techniques: dual-port interleaved DRAM architecture, two-stage pipelined circuit operation, and write before sensing. Random cycle time of 8 ns under worst-case conditions has been confirmed with a 0.25-/spl mu/m embedded DRAM test chip. This is six times faster than conventional DRAM.

Keywords

DRAM chips; integrated circuit testing; parallel memories; pipeline processing; two-port networks; 0.25 micron; 8 ns; D/sup 2/RAM; DRAM test chip; dual-port interleaved DRAM architecture; random cycle embedded RAM macro; random cycle time; two-stage pipelined circuit operation; worst-case conditions; write before sensing; Capacitors; Circuit testing; Delay; Graphics; Large scale integration; Memory architecture; Random access memory; Read-write memory; Throughput; Transistors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.881213

Filename

881213