Title :
1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro
Author :
Takahashi, Osamu ; Dhong, Sang H. ; Ohkubo, Manabu ; Onishi, Shohji ; Dennard, Robert H. ; Hannon, Robert ; Crowder, Scott ; Iyer, Subramanian S. ; Wordeman, Matthew R. ; Davari, Bijan ; Weinberger, William B. ; Aoki, Naoaki
Author_Institution :
Austin Res. Lab., IBM Corp., Austin, TX, USA
Abstract :
This embedded-DRAM macro is designed as a DRAM cache for a future gigahertz microprocessor system based on a logic-based DRAM technology. The most notable feature of this macro is its ability to run synchronously with a gigahertz CPU clock in a fully pipelined fashion. It is designed to operate with a 1-GHz clock signal at 85/spl deg/C, nominal process parameters, and a 10% degraded V/sub DD/. The design is fully pipelined and synchronous with 16 independent subarrays. With 1-kb wide I/0 and a 1-GHz clock, the maximum data rate becomes 1 Tb per second. The address access time is 3.7 ns, four cycles with a 1-GHz clock. The subarray cycle time is 12 ns.
Keywords :
DRAM chips; cache storage; cellular arrays; embedded systems; parallel memories; pipeline processing; 1 GHz; 12 ns; 3.7 ns; 85 degC; DRAM cache; address access time; data rate; embedded synchronous DRAM macro; fully pipelined fashion; gigahertz microprocessor system; independent subarrays; logic-based DRAM technology; process parameters; subarray cycle time; CMOS technology; Cache memory; Clocks; Degradation; Laboratories; Microprocessors; Random access memory; Signal design; Signal processing; System-on-a-chip;
Journal_Title :
Solid-State Circuits, IEEE Journal of
