Title :
A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F2 cell [CMOS design]
Author :
Kim, Jong-Shik ; Choi, Yu-Soo ; Yoo, Hoi-Jun ; Seo, Kwang-Seok
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
7/1/1998 12:00:00 AM
Abstract :
The 6F2 cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F2 DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F2 cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F2 cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed
Keywords :
CMOS integrated circuits; DRAM chips; VLSI; circuit stability; integrated circuit design; integrated circuit noise; memory architecture; 2 kbit; area overhead; array noise; bit-line noise absorbing scheme; bit-line to bit-line coupling noise; divided sense and combined restore scheme; folded bit-line sensing architecture; low-noise sensing scheme; multigigabit DRAM; noise reduction methods; sensing time; stable operation; total chip area; ultrahigh-density 6F2 cell; word-line to bit-line coupling noise; Capacitors; Circuit testing; Integrated circuit noise; Integrated circuit synthesis; Integrated circuit technology; Memory architecture; Noise reduction; Random access memory; Semiconductor device noise; Semiconductor optical amplifiers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
