Title :
Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS]
Author :
Moloney, David ; Brien, Jerry O. ; Rourke, Eugene O. ; Brianti, Francesco
Author_Institution :
Silicon Syst. Design Ltd., Dublin, Ireland
fDate :
7/1/1998 12:00:00 AM
Abstract :
A two-sample per cycle, programmable five-tap, area-efficient finite-impulse response (FIR) filter for hard-disk drive PRML read channels is presented. The design is optimized for low power, achieving a figure of 6.25 μW/MHz with a gate density of 2.3 K, by a combination of algorithmic, architectural, circuit-level, and layout techniques
Keywords :
BiCMOS digital integrated circuits; FIR filters; digital filters; hard discs; maximum likelihood detection; partial response channels; programmable filters; algorithmic techniques; architectural techniques; area-efficient filter; circuit-level techniques; five-tap programmable FIR filter; gate density; hard-disk drive PRML read channels; layout techniques; low-power design; two-sample per cycle filter; Algorithm design and analysis; Analog integrated circuits; BiCMOS integrated circuits; Delay; Digital signal processing; Finite impulse response filter; Hard disks; Power dissipation; Registers; Signal design;
Journal_Title :
Solid-State Circuits, IEEE Journal of
