Title :
A 12-bit medium-time analog storage device in a CMOS standard process
Author :
Ehlert, Martin ; Klar, Heinrich
Author_Institution :
Inst. of Microelectron., Tech. Univ. Berlin, Germany
fDate :
7/1/1998 12:00:00 AM
Abstract :
A new 12-bit medium-time analog storage device is presented. The proposed circuit is based on a fully differential two-stage operational amplifier (opamp) working as a sample-and-hold circuit (S&H). A novel refresh scheme employing common-mode rejection has been developed which extends the storage time on a capacitance beyond the border of voltage decay caused by charge leaking. Measurements show 12- and 8-bit resolution for 15 and 330 s, respectively, at room temperature. Compared to analog storage on a simple capacitance, the new scheme offers 84% area reduction for the same storage times while achieving much faster read-write cycle times. The circuit is intended for use in analog neural networks. The basic idea can be extended to design simple low-cost S&H circuits
Keywords :
CMOS analogue integrated circuits; neural chips; operational amplifiers; sample and hold circuits; 12 bit; 15 s; 330 s; 8 bit; CMOS standard process; analog neural networks; area reduction; charge leaking; common-mode rejection; fully differential two-stage operational amplifier; medium-time analog storage device; read-write cycle times; refresh scheme; sample-and-hold circuit; storage time; voltage decay; CMOS process; CMOS technology; Circuits; Diodes; Leakage current; Parasitic capacitance; Resistors; Sampling methods; Switches; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
