An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs

A new flexible and area-efficient VLSI architecture of a Reed-Solomon product-code decoder/encoder has been developed for digital VCRs. The new architecture of the decoder/encoder targeted to reduce the circuit size and decoding latency has the following three features. First, a high area-efficiency has been achieved by sharing a functional block for encoding, modified syndrome computation, and erasure locator polynomial evaluation. Second, the circuit size and decoding latency has been reduced by using a new architecture to implement the modified Euclid´s algorithm. Third, by doubling the internal clock speed (from 18 MHz to 36 MHz), the decoding latency and hence the memory size can be reduced. The decoder/encoder designed by using the proposed method uses a reduced number of gates, by about 30%, than the one based on the conventional architectures