Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion

Author

Shenai, Krishna

Author_Institution

Gen. Electr. Corp., Schenectady, NY, USA

Volume

37

Issue

4

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

1141

Lastpage

1153

Abstract

The systematic optimization of low-voltage silicon power MOSFET technology is described. It is shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from low-voltage silicon power MOSFETs. The details discussed include: (1) system impact; (2) unit cell optimization; (3) device and process modeling; (4) fabrication technology development; and (5) performance results. The device technologies optimized include 30-, 50-, and 100-V vertical power DMOSFETs with optimally scaled gate polysilicon and source/drain contacts. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and improved high-frequency switching performance have been fabricated with excellent wafer yield. This is the first successful demonstration of device scaling and its impact on performance of high-voltage and smart-power technologies

Keywords

elemental semiconductors; insulated gate field effect transistors; power transistors; semiconductor device models; semiconductor switches; silicon; 30 to 100 V; DMOSFETs; Si; advanced fabrication technologies; device modelling; device scaling; high-frequency power conversion; high-frequency switching performance; low resistance package; low-voltage; optimally scaled LV device; process modeling; scaled gate polysilicon; source/drain contacts; unit cell optimization; vertical power MOSFETs; Doping; Electron mobility; FETs; Fabrication; Immune system; MOSFETs; Power conversion; Power system modeling; Silicon; Surface resistance;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.52453

Filename

52453