Title :
Low-speed scan testing of charge-sharing faults for CMOS domino circuits
Author :
Cheng, C.H. ; Jone, W.B. ; Chang, S.C. ; Wang, J.S.
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Taiwan
fDate :
9/28/2000 12:00:00 AM
Abstract :
Domino circuits have been widely used to design high-performance processors. However, domino logic suffers from the problem of charge-sharing, which may degrade the output voltage level or even cause an erroneous output value (charge-sharing fault). It is shown that charge-sharing faults are resistant to scan testing and that a killing error might occur because of the low-speed testing problem caused by scan testing. The testing error is investigated and a DFT technique to efficiently eliminate this problem is proposed
Keywords :
CMOS logic circuits; design for testability; integrated circuit testing; logic design; logic testing; CMOS domino circuits; DFT technique; charge-sharing faults; domino logic; low-speed scan testing; testing error;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20001203
