Compilers for instruction-level parallelism

Author

Schlansker, Michael ; Conte, Thomas M. ; Dehnert, J. ; Ebcioglu, Kemal ; Fang, Jesse Z. ; Thompson, Carol L.

Author_Institution

Hewlett-Packard Labs., Palo Alto, CA, USA

Volume

30

Issue

12

fYear

1997

fDate

12/1/1997 12:00:00 AM

Firstpage

63

Lastpage

69

Abstract

Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance. What technical challenges must compiler writers meet to better use ILP? Instruction level parallelism allows a sequence of instructions derived from a sequential program to be parallelized for execution on multiple pipelined functional units. If industry acceptance is a measure of importance, ILP has blossomed. It now profoundly influences the design of almost all leading edge microprocessors and their compilers. Yet the development of ILP is far from complete, as research continues to find better ways to use more hardware parallelism over a broader class of applications

Keywords

instruction sets; parallel architectures; parallel programming; parallelising compilers; ILP; compiler writers; hardware parallelism; industry acceptance; instruction level parallelism; leading edge microprocessors; microprocessor performance; multiple pipelined functional units; sequential program; technical challenges; Application software; Computer architecture; Hardware; Job shop scheduling; Microprocessors; Optimizing compilers; Parallel processing; Processor scheduling; Program processors; VLIW;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.642817

Filename

642817