Plasma damage immunity of thin gate oxide grown on very lightly N/sup +/ implanted silicon

Author

Cheung, K.P. ; Misra, D. ; Colonell, J.I. ; Liu, C.T. ; Ma, Y. ; Chang, C.P. ; Lai, W.Y.C. ; Liu, R. ; Pai, C.S.

Author_Institution

Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA

Volume

19

Issue

7

fYear

1998

fDate

7/1/1998 12:00:00 AM

Firstpage

231

Lastpage

233

Abstract

Plasma damage immunity of gate oxide grown on very low dose (2/spl times/10/sup 13//cm/sup 2/) N/sup +/ implanted silicon is found to be improved compared to a regular gate oxide of similar thickness. Both hole trapping and electron trapping are suppressed by the incorporation of nitrogen into the gate oxide. Hole trapping behavior was determined from the relationship between initial electron trapping slope (IETS) and threshold voltage shifts due to current stress. This method is believed to be far more reliable than the typical method of initial gate voltage lowering during current stress.

Keywords

electron traps; elemental semiconductors; hole traps; ion implantation; nitrogen; oxidation; semiconductor doping; silicon; Si:N; SiO; current stress; electron trapping; hole trapping; initial electron trapping slope; lightly N/sup +/ implanted silicon; plasma damage immunity; thin gate oxide; threshold voltage shifts; CMOS technology; Charge carrier processes; Electron traps; Implants; Measurement uncertainty; Nitrogen; Plasma measurements; Silicon; Stress; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.701426

Filename

701426