A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. The dopant in the source-drain extension is assumed to segregate to the Si/SiO/sub 2/ interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail,.