High-temperature latchup characteristics in VLSI CMOS circuits

Author

Shoucair, F.S.

Author_Institution

Dept. of Electr. Eng., Brown Univ., Providence, RI, USA

Volume

35

Issue

12

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

2424

Lastpage

2426

Abstract

A simple worst-case analytical model of holding currents and an empirical model of trigger currents are reported and shown to agree with experimental measurements in the range of 25-225°C. Whereas standard bulk CMOS inverters and ring oscillators are invariably found to latchup near 125°C, their counterparts built on epitaxial wafers remain latchup free up to at least 250°C. These results add to an ongoing systematic effort to model high-temperature effects in integrated MOS technologies and provide worst case latchup information in the commercial temperature range and beyond

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; logic gates; oscillators; semiconductor device models; semiconductor epitaxial layers; 25 to 250 C; CMOS ring oscillators; VLSI CMOS circuits; commercial temperature range; empirical model; epitaxial CMOS invertors; epitaxial wafers; experimental measurements; high temperature latchup characteristics; high-temperature effects; holding currents; integrated MOS technologies; standard bulk CMOS inverters; trigger currents; worst case latchup information; worst-case analytical model; Analytical models; CMOS technology; Current measurement; Integrated circuit measurements; Inverters; Ring oscillators; Semiconductor device modeling; Semiconductor process modeling; Thermal factors; Very large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.8826

Filename

8826