Analysis of enhanced hot-carrier effects in scaled flash memory devices

Author

Chen, Chun ; Liu, Zhi-Zheng ; Ma, T.P.

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA

Volume

45

Issue

7

fYear

1998

fDate

7/1/1998 12:00:00 AM

Firstpage

1524

Lastpage

1530

Abstract

In this paper, we analyze the impact of both junction scaling and channel length scaling on hot-carrier reliability of Flash memory devices with the help of a newly developed charge pumping technique. Lateral profiles of dopant concentration and erase-induced damage near both graded and abrupt junctions were obtained from charge pumping measurements. We found that more erase-induced damage is spread into the channel if the junction Is more abrupt. Further current-voltage (I-V) measurements and write/erase cycling experiments demonstrate that the effect of erase-induced damage on V_t becomes more severe when channel length is scaled down. To scale down Flash memory devices without sacrificing reliability, we suggest to either keep the source junction sufficiently graded or reduce the erase source bias

Keywords

CMOS memory circuits; EPROM; doping profiles; hot carriers; integrated circuit reliability; abrupt junction; channel length scaling; charge pumping measurement; current-voltage measurement; dopant profile; erase-induced damage; flash memory device; graded junction; hot carrier reliability; junction scaling; threshold voltage; write/erase cycling; Charge measurement; Charge pumps; Current measurement; EPROM; Electrodes; Fault location; Flash memory; Hot carrier effects; Nonvolatile memory; Tunneling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.701484

Filename

701484