A high-performance encoder with priority lookahead

Author

Delgado-Frias, José G. ; Nyathi, Jabulani

Author_Institution

Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA

Volume

47

Issue

9

fYear

2000

fDate

9/1/2000 12:00:00 AM

Firstpage

1390

Lastpage

1393

Abstract

In this brief, we introduce a priority encoder that uses a novel priority lookahead (PL) scheme to reduce delays associated with priority propagation. Two priority encoder approaches are presented, one without and the other with a PL scheme. For an N-bit encoder, the circuit with the PL scheme requires about 0.1 more transistors than the circuit without the scheme. However, a 32-bit very large scale integration (VLSI) encoder with the PL scheme is about 2.5 times faster than the other encoder. The worst case operation delay is 4.4 ns for this lookahead encoder using a 1 μm scalable complementary metal-oxide-semiconductor (CMOS) technology.

Keywords

CMOS logic circuits; VLSI; carry logic; delays; high-speed integrated circuits; 1 micron; 32 bit; 4.4 ns; VLSI; delays; high-performance encoder; priority lookahead; priority propagation; scalable complementary metal-oxide-semiconductor technology; worst case operation; Application software; CMOS technology; Circuits; Equations; Hardware; Logic; Multiprocessor interconnection networks; Propagation delay; Very large scale integration; Wiring;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.883335

Filename

883335