Linear CMOS triode transconductor for low-voltage applications

A linear transconductor is presented which uses transistors biased in the triode region. Based on the regulated-cascode technique for maintaining the drain-source voltage of triode-biased transistors. The circuit offers an advantage in terms of a low supply requirement, resulting from the use of a short-channel pMOS transistor for the gain stage. Analysis and design considerations for optimising the large-signal characteristic are described. The simulated THD of the proposed circuit is smaller than -56 dB for differential input ranges up to 0.8 V_peak at 3 V for the entire transconductance tuning range