Is a New Paradigm for Nanoscale Analog CMOS Design Needed?

Nanoscale analog CMOS IC design productivity is becoming a major concern for the semiconductor industry as chip device counts approach 1 billion at 32 nm and each technology offers a choice of several operating platform variants. A multitude of physical device pattern separation dimensions must now be entered into the prelayout simulation models in order to predict postlayout circuit performance accurately. The random nature of analog physical design, which focuses on signal flow and coupling, increases the randomness and difficulty of prelayout simulation parameter entry. A new paradigm for analog circuit and physical design is presented which relies on restrictive design rules for device physical design.