Title :
A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique
Author :
Huang, Yen-Chuan ; Lee, Tai-Cheng
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
6/1/2011 12:00:00 AM
Abstract :
A 10-bit pipelined ADC employs both opamp-and time-sharing techniques to reduce the power consumption and silicon area. The proposed ADC needs only one opamp to complete the 10-bit conversion. This ADC has been fabricated in a 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0-V supply.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; operational amplifiers; time-sharing systems; SNDR; digital CMOS technology; operational amplifier; pipelined ADC; power 4.5 mW; power consumption reduction; silicon area; size 90 nm; time-sharing technique; voltage 1 V; word length 10 bit; Accuracy; Capacitance; Capacitors; Loading; Noise; Power demand; Switches; Capacitor-sharing technique; opamp-sharing technique; pipelined ADC; time-sharing technique;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2010.2092170
