0.2-μm fully-self-aligned Y-shaped gate HJFET´s with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-μm, high-aspect-ratio, Y-shaped-gate heterojunction-FET´s (HJFET´s) with about half the external gate-fringing capacitance (C_f^rext) of conventional Y-shaped gate HJFET´s. The 0.2-μm Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO₂ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-μm gate n-Al_0.2Ga_0.8As/In_0.2Ga_0.8As HJFET shows very small current saturation voltage of 0.25 V, marked gm _max of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f_T=71 GHz and f_max=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C_f^rext. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC´s/LSI´s