On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter

Author

Jin, Wei ; Chan, Mansun ; Mansun Chan

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong

Volume

45

Issue

8

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

1717

Lastpage

1724

Abstract

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V

Keywords

MOSFET; logic gates; silicon-on-insulator; 0.7 V; SOI dynamic threshold voltage MOSFET inverter; device parasitic capacitance; dynamic threshold silicon-on-insulator CMOS inverter; gate delay; load capacitance; long-channel DC model; power dissipation model; short-circuit power dissipation; static power dissipation; switching power dissipation; Delay; Inverters; MOSFET circuits; Parasitic capacitance; Power MOSFET; Power dissipation; Power supplies; Semiconductor device modeling; Silicon on insulator technology; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.704370

Filename

704370