Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

Author

Kamath, Aashit ; Chen, Zhixian ; Shen, Nansheng ; Singh, Navab ; Lo, G.Q. ; Kwong, Dim-Lee ; Kasprowicz, Dominik ; Pfitzner, Andrzej ; Maly, Wojciech

Author_Institution

Inst. of Microelectron., Agency for Sci., Technol. & Res., Singapore, Singapore

Volume

33

Issue

2

fYear

2012

Firstpage

152

Lastpage

154

Abstract

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high I_ON/I_OFF ratio (>; 10⁶). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

Keywords

CMOS logic circuits; MOSFET; NAND circuits; logic gates; AND function; CMOS NAND logic implementation; MOS transistor; OR function; device architecture; device fabrication; fabrication-based feasibility assessment; junctionless vertical-slit field-effect transistor; slit width variation; Fabrication; FinFETs; Logic circuits; Logic gates; Performance evaluation; Silicon; and and or logic functions; independent gate; junctionless device; logic circuits; multifunctionality; vertical-slit field-effect transistors (VeSFETs);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2176309

Filename

6112177