Design and Analysis of a Class-D Stage With Harmonic Suppression

This paper presents the design and analysis of a low-power Class-D stage in 90 nm CMOS featuring a harmonic suppression technique, which cancels the 3rd harmonic by shaping the output voltage waveform. Only digital circuits are used and the short-circuit current present in Class-D inverter-based output stages is eliminated, relaxing the buffer requirements. Using buffers with reduced drive strength for the output stage reduces the 5th harmonic at the output, as the rise and fall time of the output voltage increase. Operating at 900 MHz, the measured output power was +5.1 dBm with drain efficiency (DE) and power-added efficiency (PAE) of 73% and 59% at 1.2 V. The 3rd and 5th harmonics were suppressed by 34 dB and 4 dB, respectively, compared to an inverter-based Class-D stage.