DocumentCode :
1408073
Title :
Improved Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultrathin Oxide Partially Depleted SOI Floating-Body CMOS
Author :
Chen, David C. ; Lee, Ryan ; Liu, Yuan-Chang ; Lin, Guan-Shyan ; Tang, Mao-Chyuan ; Wang, Meng-Fan ; Yeh, Chune-Sin ; Chien, Shan-Chieh
Author_Institution :
Adv. Technol. Dev. Div., United Microelectron. Corp., Hsinchu, Taiwan
Volume :
25
Issue :
2
fYear :
2012
fDate :
5/1/2012 12:00:00 AM
Firstpage :
155
Lastpage :
161
Abstract :
Device scaling of partially depleted (PD) silicon-on-insulator (SOI) has the potential to increase speed. However, the increased gate tunneling and capacitance will complicate device behaviors and increase the difficulty in characterization for modeling purpose. For the first time, gate-bulk leakage current Igb and gate capacitance Cgg characterization methodology for PD SOI floating-body (FB) CMOS with high accuracy is proposed and verified in 40-nm SOI devices. These devices are with ultrathin equivalent oxide thickness of 12Å, and radio frequency-capacitance voltage (RF-CV) technique is used for Cgg measurement to overcome the impact of leaky gate current. This methodology can eliminate properly the parasitic elements due to the coexistence of opposite poly gate type in the SOI T-shape body-tied device and accurately characterize and model Igb and Cgg behaviors for the PD SOI FB devices. Test patterns are designed with RF ground-signal-ground configuration and same test patterns can be used for both Igb and Cgg characterization. Impact of Igb and Cgg changes on the history effect, and speed and body potential is analyzed by BSIMSOI4.0 models. Simulation accuracy of history effect will have at least 3% improvement with this proposed methodology.
Keywords :
CMOS integrated circuits; automatic test pattern generation; capacitance; integrated circuit modelling; leakage currents; silicon-on-insulator; tunnelling; BSIMSOI4.0 models; PD SOI FB devices; PD SOI floating-body CMOS; RF ground-signal-ground configuration; RF-CV technique; SOI T-shape body-tied device; SOI devices; device behaviors; device scaling; gate capacitance characterization methodology; gate tunneling; gate-bulk leakage current; history effect; improved characterization methodology; leaky gate current; opposite poly gate type; parasitic elements; partially depleted silicon-on-insulator; radio frequency-capacitance voltage technique; test patterns; ultrathin equivalent oxide thickness; ultrathin oxide partially depleted SOI floating-body CMOS; Calibration; Capacitance; Delay; History; Logic gates; MOSFET circuits; Radio frequency; Gate capacitance; RF-CV; gate leakage; history effect; silicon-on-insulator (SOI);
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2011.2181668
Filename :
6112247
Link To Document :
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