DocumentCode :
1408106
Title :
Design of an inner-product processor for hardware realization of multi-valued exponential bidirectional associative memory
Author :
Wang, Chua-Chin ; Huang, Chenn-Jung ; Chen, Ying-Pei
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume :
47
Issue :
11
fYear :
2000
fDate :
11/1/2000 12:00:00 AM
Firstpage :
1271
Lastpage :
1278
Abstract :
Inner-product calculations are often required in digital neural computing. The critical path of the inner product of two vectors is the carry propagation delay generated from individual product terms. In this work, a novel and high-speed realization of an inner-product processor for the multi-valued exponential bidirectional associative memory (MV-eBAM) is presented in order to reduce the carry propagation delay, wherein the treatment of inner product of two vectors is given. Notably, a systolic-like architecture of digital compressors is used to reduce the carry propagation delay in the critical path of the inner product of two vectors. The architecture we propose here might offer a sub-optimal solution for the digital hardware realization of the inner-product computation.
Keywords :
content-addressable storage; delays; digital arithmetic; multiplying circuits; performance evaluation; systolic arrays; bidirectional associative memory; carry propagation delay; digital compressors; digital neural computing; hardware realization; high-speed realization; inner-product processor; multi-valued exponential associative memory; propagation delay reduction; systolic-like architecture; Associative memory; Compressors; Computer architecture; Computer networks; Magnesium compounds; Neural network hardware; Neural networks; Propagation delay; Very large scale integration; Voltage;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.885133
Filename :
885133
Link To Document :
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