DocumentCode :
1408308
Title :
Resonance and damping in CMOS circuits with on-chip decoupling capacitance
Author :
Larsson, Patrik
Author_Institution :
Bell Labs., Lucent Technol., Holmdel, NJ, USA
Volume :
45
Issue :
8
fYear :
1998
fDate :
8/1/1998 12:00:00 AM
Firstpage :
849
Lastpage :
858
Abstract :
Design of on-chip decoupling capacitance and modeling of resonance effects in the power supply network of CMOS integrated circuits is addressed. The modeling is based on mathematical limits proving that damping will be low, resulting in resonance unless careful design is used. Design strategies that reduce resonance are discussed. It is shown that an optimal parasitic resistor in series with the decoupling capacitor gives a maximum damping factor of 0.5 and practical values are within the range 0.3-0.4. Examples of digital circuits show that proper design of on-chip decoupling capacitance may reduce the number of bonding wires by an order of magnitude. The modeling and design suggestions are also applicable to mixed-mode circuits. In particular, sampled analog networks benefit with a potentially higher sampling rate if enhanced damping is introduced during design
Keywords :
CMOS integrated circuits; capacitance; circuit resonance; damping; integrated circuit design; integrated circuit modelling; integrated circuit noise; power supply circuits; CMOS circuit; bonding wire; damping; design; digital circuit; mixed-mode circuit; model; on-chip decoupling capacitance; parasitic resistor; power supply network; resonance; sampled analog network; CMOS integrated circuits; Capacitance; Damping; Integrated circuit modeling; Mathematical model; Network-on-a-chip; Power supplies; RLC circuits; Resonance; Semiconductor device modeling;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7122
Type :
jour
DOI :
10.1109/81.704824
Filename :
704824
Link To Document :
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