Title :
A bit-level pipelined VLSI architecture for the running order algorithm
Author :
Chen, Chun-Te ; Chen, Liang-Gee ; Hsiao, Jue-Hsuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
8/1/1997 12:00:00 AM
Abstract :
A bit-level pipelined VLSI architecture for the running order algorithm is presented. Based on the proposed modified algorithm, the deletion and the insertion is successfully pipelined in the bit-level operation. A block processing architecture of this modified algorithm is also constructed. The pipelined cycle of the proposed architecture is merely equivalent to the delay time of a pair of 1-bit comparisons that is independent on the window size and the signal resolution
Keywords :
VLSI; digital signal processing chips; pipeline arithmetic; 1-bit comparisons; bit level operation; bit level pipelined VLSI architecture; block processing architecture; delay time; deletion; insertion; modified algorithm; nonlinear filtering; pipelined cycle; running order algorithm; Delay effects; Filtering; Hardware; Nonlinear filters; Parallel processing; Pipelines; Signal processing algorithms; Signal resolution; Throughput; Very large scale integration;
Journal_Title :
Signal Processing, IEEE Transactions on
