Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in the quasi-2-D Poisson model. The proposed model correctly predicts the effects of drain bias (V_DS), counter doping layer thickness (x_CD), counter doping concentration (N_CD), substrate doping concentration (N_sub) and source/drain junction depth (x_j), and the new model performs satisfactorily in the sub-0.1 μm regime. By using the proposed model on the threshold voltage reduction and subthreshold swing, we have obtained the process windows of the counter doping thickness and the substrate concentration. These process windows are very useful for predicting the scaling limit of the buried channel pMOSFET with known process conditions or systematic design of the buried channel pMOSFET.