Title :
Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells
Author :
Durrani, Zahid Ali Khan ; Lnine, A.C. ; Ahmed, Haroon
Author_Institution :
Cavendish Lab., Cambridge Univ., UK
fDate :
12/1/2000 12:00:00 AM
Abstract :
A 3×3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 μm×1 μm or 1 μm×70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write/read operation for a selected cell within the array is demonstrated. The measured states are separated by ∼1000 electrons for the 1 μm×1 μm memory node cell and by 60 electrons for the 1 μm×70 nm memory node cell. Single-electron transistor controlled operation persists up to a temperature of 65 K.
Keywords :
Coulomb blockade; MOSFET; silicon-on-insulator; single electron transistors; 1 mum; 65 K; 70 nm; Coulomb blockade memory; integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells; silicon-on-insulator; write/read operation; Integrated circuit measurements; MOSFET circuits; Magnetic tunneling; Memory architecture; Random access memory; Semiconductor materials; Silicon on insulator technology; Single electron transistors; Split gate flash memory cells; Temperature control;
Journal_Title :
Electron Devices, IEEE Transactions on
