A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

Author

Chen, Ming-Shuan ; Shih, Yu-Nan ; Lin, Chen-Lun ; Hung, Hao-Wei ; Lee, Jri

Author_Institution

Electr. Eng. Dept., Nat. Taiwan Univ., Taipei, Taiwan

Volume

47

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

627

Lastpage

640

Abstract

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and data recovery circuit using majority voting phase detection. The transceiver delivers 40-Gb/s 2⁷-1 PRBS data across a Rogers channel of 20 cm (19-dB loss at 20 GHz) with BER <; 10^-12 while consuming a total power of 655 mW.

Keywords

CMOS integrated circuits; FIR filters; clock and data recovery circuits; closed loop systems; delay lines; error statistics; radio transceivers; 5-tap finite-inpulse response filter; CMOS technology; LC-based delay lines; Rogers channel; bit error rate; bit rate 40 Gbit/s; clock and data recovery circuit; closed-loop delay controller; digital adaptation; equalizer front-end; majority voting phase detection; power 655 mW; radio tansceiver; size 65 nm; wireline transceiver; Bandwidth; CMOS integrated circuits; Clocks; Delay; Finite impulse response filter; Power transmission lines; Transceivers; Clock and data recovery (CDR); equalizer; finite-inpulse response (FIR) filter; majority voting; transceiver (TRx);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2011.2176635

Filename

6117094