DocumentCode :
1411152
Title :
Analyzing packaging trade-offs during system design
Author :
Sandborn, Peter A. ; Vertal, Mike
Author_Institution :
Dept. of Mech. Eng., Maryland Univ., College Park, MD, USA
Volume :
15
Issue :
3
fYear :
1998
Firstpage :
10
Lastpage :
19
Abstract :
Integrating packaging trade-off analysis with functional verification and architectural design results in a complete virtual prototyping solution far optimizing complex electronic systems. The authors discuss the role of packaging costs in system design and present examples highlighting packaging design trade-offs
Keywords :
packaging; architectural design; functional verification; packaging design; packaging trade-off; virtual prototyping; Computer architecture; Cost function; Design optimization; Electronic equipment testing; Electronics packaging; Feedback; Hardware; System analysis and design; System testing; Virtual prototyping;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.706028
Filename :
706028
Link To Document :
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