Title :
Testability features of the AMD-K6 microprocessor
Author :
Fetherson, R.S. ; Shak, I.P. ; Ma, Siyad C.
Author_Institution :
Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
The AMD-K6´s embedded design-for-testability structures and test pattern development methodologies provide high-quality manufacturing tests. The DFT features support static voltage-level testing for wafer-sort and debug testing, application of two pattern sequences for detection of timing-related failures, scan-based BIST, and 1149.1 boundary scan
Keywords :
built-in self test; computer testing; microprocessor chips; AMD-K6 microprocessor; boundary scan; debug testing; design-for-testability; scan-based BIST; test pattern development; timing-related failures; voltage-level testing; wafer-sort; Buffer storage; CMOS technology; Centralized control; Clocks; Computer aided manufacturing; Decoding; Isolation technology; Logic; Microprocessors; Testing;
Journal_Title :
Design & Test of Computers, IEEE
