Optimization and Analysis of the Dual n/p-LDMOS Device

Author

Poli, Stefano ; Reggiani, Susanna ; Sharma, Rupendra Kumar ; Denison, Marie ; Gnani, Elena ; Gnudi, Antonio ; Baccarani, Giorgio

Author_Institution

Adv. Res. Center for Electron. Syst. E. De Castro, Univ. of Bologna, Bologna, Italy

Volume

59

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

745

Lastpage

753

Abstract

A scalable Dual n/p-LDMOS device with interesting R_SP versus V_BD performance for voltage applications in the range of 20-120 V is identified through proper optimization. Three designs have been proposed, based on different process implementations. The physical behavior of the device is reviewed and analyzed. The current expansion induced by the bipolar conductance in the drift region at high gate and drain biases is fully explained. The thermal behavior in a worst case condition is investigated, and the reduction in performance in terms of current and safe-operating area are reported. The switching performance is addressed, showing very good transient times in any analyzed load condition.

Keywords

MIS devices; bipolar conductance; drain bias; drift region; dual n/p-LDMOS device; gate bias; load condition; physical behavior; process implementations; switching performance; thermal behavior; voltage 20 V to 120 V; voltage applications; Charge carrier processes; Doping; Implants; Logic gates; Modulation; Optimization; Transistors; High-field effects; lateral DMOS (LDMOS); super junction (SJ);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2178189

Filename

6118322