Low voltage Manchester adder design

A low voltage dynamic Manchester adder design is presented, with a critical delay path operating at a higher voltage level. This voltage level is generated on-chip using a bootstrapping circuit. The goal of this design is to maintain the delay of its worst-case path, comparable to the design having a higher supply voltage, while operating the rest of the circuit at a lower supply voltage, thus consuming less overall power. A SPICE simulation is performed to verify the design