Title :
Will physical scalability sabotage performance gains?
Author_Institution :
Texas Instrum. Inc., USA
fDate :
9/1/1997 12:00:00 AM
Abstract :
The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will soon be impossible to maintain one global clock over the entire chip, and sending signals across a billion-transistor processor may require as many as 20 cycles
Keywords :
ULSI; clocks; delays; microprocessor chips; performance evaluation; technological forecasting; ULSI; chip architects; clock cycles; data transmission speed; feature size; global clock; on-chip devices; on-chip wires; performance gains; physical scalability; signalling; wire delays; CMOS process; Clocks; Delay effects; Drives; Instruments; Performance gain; Process design; Scalability; Transistors; Wire;
