Title :
Two-step split-junction SAR ADC
Author :
Yu, Weimin ; Lin, James ; Temes, Gabor C.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Abstract :
A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analogue-to-digital converters (SAR ADCs). Two split-junction binary-weighted capacitor arrays are used in a coarse/fine quantisation scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC.
Keywords :
analogue-digital conversion; capacitors; power consumption; SAR ADC; capacitor area; coarse/fine quantisation scheme; power consumption; successive-approximation register analogue-to-digital converter; two split-junction binary-weighted capacitor arrays;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.2392
