DocumentCode :
1415469
Title :
Efficient unfolding procedure for DSP applications
Author :
Kim, J.
Author_Institution :
Centre for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
Volume :
34
Issue :
16
fYear :
1998
fDate :
8/6/1998 12:00:00 AM
Firstpage :
1552
Lastpage :
1554
Abstract :
An FSFG can be used to obtain a rate-optimal schedule. There are some criteria to measure the optimality. Normally, an iteration period bound (IPB) is used for the optimal implementation. If an iteration period (IP) is the same as the IPB, the schedule is called rate-optimal. Unfolding can reduce the IP and guarantee rate-optimal schedules with an optimum unfolding factor. A new unfolding procedure, called JK´s unfolding, is introduced which has low complexity and can be described using graphical methods
Keywords :
VLSI; digital signal processing chips; flow graphs; iterative methods; processor scheduling; DSP applications; FSFG; JK´s unfolding; fully-specified flow graph; graphical methods; iteration period bound; optimality; rate-optimal schedule; rate-optimal schedules; unfolding procedure;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19981119
Filename :
707127
Link To Document :
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