DocumentCode
1415521
Title
The MAJC architecture: a synthesis of parallelism and scalability
Author
Tremblay, Marc ; Chan, Jeffrey ; Chaudhry, Shailender ; Conigliam, A.W. ; Tse, Shing Sheung
Author_Institution
Sun Microsyst
Volume
20
Issue
6
fYear
2000
Firstpage
12
Lastpage
25
Abstract
The MAJC architecture enhances application performance by exploiting parallelism at multiple levels-instruction, data, thread, and process. Supporting vertical multithreading, speculative multithreading, and chip multiprocessors, the scalable VLIW architecture is also capable of advanced speculation and predication and treats all data types similarly
Keywords
multi-threading; multiprocessing systems; parallel architectures; MAJC architecture; chip multiprocessors; data types; multithreading; parallelism; scalability; scalable VLIW architecture; speculative multithreading; vertical multithreading; Communication system control; Computer architecture; Java; Microprocessors; Multithreading; Parallel processing; Registers; Scalability; Sun; VLIW;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/40.888700
Filename
888700
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