DocumentCode :
1415549
Title :
An advanced optimizer for the IA-64 architecture
Author :
Krishnaiyer, Rakesh ; Kulkami, D. ; Laven, D. ; Wei, Lan ; Lim, Chu-cheow ; Ng, John ; Sehr, David
Author_Institution :
Microcomput. Software Labs., Intel Corp., Santa Clara, CA, USA
Volume :
20
Issue :
6
fYear :
2000
Firstpage :
60
Lastpage :
68
Abstract :
The IA-64 architecture´s rich set of features enable aggressive high-level and scalar optimizations-supported by the latest analysis techniques-to improve integer and floating-point performance
Keywords :
floating point arithmetic; microprocessor chips; performance evaluation; IA-64 architecture; floating-point performance; high-level optimization; integer performance; scalar optimizations; Application software; Delay; Information analysis; Optimizing compilers; Parallel processing; Performance analysis; Prefetching; Processor scheduling; Program processors; Registers;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/40.888704
Filename :
888704
Link To Document :
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