• DocumentCode
    1415552
  • Title

    Two´s complement parallel multiplier

  • Author

    Aggoun, A.

  • Author_Institution
    Fac. of Comput. Sci. & Eng., De Montfort Univ., Leicester, UK
  • Volume
    34
  • Issue
    16
  • fYear
    1998
  • fDate
    8/6/1998 12:00:00 AM
  • Firstpage
    1570
  • Lastpage
    1571
  • Abstract
    A new two´s complement parallel multiplier architecture is proposed. It is based on the partitioning of one of the operands into four groups. Array multipliers without the final adder are used to produce eight partial product terms. This allows more efficient use of 4:2-compressors in the intermediate stages. It is shown that the proposed multiplier has better performance than existing designs with respect to both area and speed
  • Keywords
    carry logic; multiplying circuits; parallel architectures; array multipliers; carry save adders; multiplier architecture; operand partitioning; partial product terms; two´s complement parallel multiplier;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19981142
  • Filename
    707142
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1415552