Enhancing automatic generation of VHDL descriptions from UML/MARTE models

This work aims to assist the design of FPGA-based embedded system by extending the AMoDE-RT approach in order to support automatic generation of VHDL descriptions from high-level specification of embedded systems. For that, this work proposes a new set of mapping rules to translate UML/-MARTE elements into VHDL constructs, allowing the generation of fully synthesizable descriptions, including the embedded system structure and behavior. The proposed mapping rules have been implemented in GenERTiCA tool, which is used in AMoDE-RT to generate source code from UML/MARTE models, enabling the UML-to-VHDL automatic transformation. The proposed approach has been validated using a valve control system as case study. The obtained results show a decrease in FPGA used area, as well as a small impact on system performance. These results indicate the practicability of a full translation from UML elements into VHDL, opening room for specifying the system behavior using higher abstraction levels even for FPGA-based embedded system implementation.