Title :
Residual thermomechanical stresses in thinned-chip assemblies
Author :
Leseduarte, Sergio ; Marco, Santiago ; Beyne, Eric ; Van Hoof, Rita ; Marty, Antoine ; Pinel, Stéphane ; Vendier, Olivier ; Coello-Vera, Augustín
Author_Institution :
Dept. d´´Electron., Barcelona Univ., Spain
fDate :
12/1/2000 12:00:00 AM
Abstract :
A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this work, we present the first-level UTCS structure and the analysis of the thermomechanical stresses produced by the manufacturing process. Chips are thinned up to 10 or 15 μm. We discuss potentially critical points at the edges of the chips, the suppression of delamination problems of the peripheral dielectric matrix and produce a comparative study of several technological choices for the design of metallic interconnect structures. The purpose of these calculations is to give inputs for the definition of design rules for this technology. We have therefore undertaken a programme that analyzes the influence of sundry design parameters and alternative development options. Numerical analyses are based on the finite element method
Keywords :
delamination; finite element analysis; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; thermal stresses; 10 micron; 15 micron; 3D stacking; Esprit Project 24910; delamination problems; design parameters; design rules; finite element method; first-level UTCS structure; manufacturing process; metallic interconnect structures; peripheral dielectric matrix; residual thermomechanical stresses; thinned-chip assemblies; ultrathin chip stacking; Assembly; Delamination; Dielectrics; Finite element methods; Manufacturing processes; Numerical analysis; Residual stresses; Stacking; Thermal stresses; Thermomechanical processes;
Journal_Title :
Components and Packaging Technologies, IEEE Transactions on
DOI :
10.1109/6144.888852
