• DocumentCode
    1416517
  • Title

    Energy and Performance Models for Synchronous and Asynchronous Communication

  • Author

    Stevens, Kenneth S. ; Golani, Pankaj ; Beerel, Peter A.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Utah, Salt Lake City, UT, USA
  • Volume
    19
  • Issue
    3
  • fYear
    2011
  • fDate
    3/1/2011 12:00:00 AM
  • Firstpage
    369
  • Lastpage
    382
  • Abstract
    Communication costs, which have the potential to throttle design performance as scaling continues, are mathematically modeled and compared for various pipeline methodologies. First-order models are created for common pipeline protocols, including clocked flopped, clocked time-borrowing latch, asynchronous two-phase, four-phase, delay-insensitive, single-track, and source synchronous. The models are parameterized for throughput, energy, and bandwidth. The models share common parameters for different pipeline protocols and implementations to enable a fair apple-to-apple comparison. The accuracy of the models are demonstrated for complete implementations of a subset of the protocols by applying 65-nm process simulated parameter values against the SPICE simulation of full pipeline implementations. One can determine when asynchronous communication is superior at the physical level to synchronous communication in terms of energy for a given bandwidth by applying actual or expected values of the parameters to various design targets. Comparisons between protocols at fixed targets also allow designers to understand tradeoffs between implementations that have a varying process, timing, and design requirements.
  • Keywords
    SPICE; integrated circuit interconnections; integrated circuit modelling; pipeline processing; SPICE simulation; asynchronous communication; energy models; performance models; pipeline methodologies; pipeline protocols; Asynchronous; bundled-data; bundling data constraint; communication bandwidth; delay-insensitive; single-track;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2009.2037327
  • Filename
    5411948