Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applications

Power consumption is the most important issue in circuit design nowadays, and clock gating is the most widely used technique to reduce the dynamic power at register transfer level. The traditional clock gating style using an XOR gate to generate a gated clock was proposed but has not been well studied. It can be extended to multiple flip-flops easily but the power performance is not optimal. In this study, the authors propose a fine-grained activity-driven optimised bus-specific-clock-gating for ultra-low-power smart spaces applications, which can selectively choose qualified flip-flops to be gated based on their output switching activities to optimise the power. This technique has been experimented on ISCAS´89 benchmark circuits, and average power can be reduced by 19.21%.