Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

An empirical study is conducted to analyze the fault models of CMOS gates in VLSI. The mutation analysis methodology is used to ensure the simulation experiments are sufficient enough. For the primitive CMOS logic cells: inverter, 2-input NAND, NOR and XOR gates, a total of 335 mutant circuits are generated, simulated and analyzed. Comparing with the previous work, several new fault models are revealed, such as other-logic and the indetermination fault categorys sub-categories: 0-to-X, 1-to-X and other-to-X. Besides, the experimental results show that the classic static stuck-at fault cannot cover many practical defects in a circuit since it just averagely accounts for less than 15% of the total faults. Many other useful conclusions are drawn, which may benefit the related fault-based applications.